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data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 8192 mb ddr3 l C sdram ecc dimm 240 pin unbuffered ecc dimm s l u0 8 g 72k1 b d 2sa - xx r t 8 g b yte in fbga techn ology rohs compliant the refresh rate has to be doubled when 85c data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 this swissbit module is an industry standard 240 - pin 8 - byte ddr3 sdram dual - in - line memory module ( u dimm) which is organized as x 72 high speed cmos memory arrays. the module uses internally configured oct al - bank ddr3 sdram devices. the module uses double data rate architecture to achieve high - speed operation. ddr3 sdram modules operate from a differential clock (ck and ck#). read and write accesses to a ddr3 sdram module is burst - oriented; accesses start at a selected location and c ontinue for a programmed number of locations in a programmed sequence. the burst length is either four or eight locations. an auto precharge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the d dr3 sdram devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. a self refresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_ 15 compatible. the module can operate either at ddr3 mode (1.50v vdd) or ddr3l mode (1.35v vdd) the ddr3 sdram module uses the serial presence detect (spd) function implemented via serial eeprom using the standard i2c protocol. this nonvolatile storage dev ice contains 256 bytes. the first 128 bytes are utilized by the dimm manufacturer (swissbit) to identify the module type, the modules organization and several timing parameters. the second 128 bytes are available to the end user. module configuration organization ddr3 sdrams used row addr. device bank addr. col umn addr. refresh module bank select 1g x 72 bit 1 8 x 512 m x 8bit ( 4 g bit) 16 ba0, ba1, ba2 10 8k s0#, s1# module dimensions in mm 133.35 (long) x 18.75 (high) x 4. 00 [max] (thickness) timing parameters part number module density transfer rate clock cycle /data bit rate latency s l u08g72 k1bd 2sa - ccrt 8 gbyte 10.6 gb/s 1.5ns/1333mt/s 9 - 9 - 9 slu08g72k1bd2sa - dcrt 8gbyte 12.8 gb/s 1.25ns/1600mt/s 11 - 11 - 11 pin name a0 C a9 , a11 C a1 5 address inputs a10/ap address input / autoprecharge bit a12/bc# address input / burst chop ba0 C ba 2 bank address inputs dq0 C dq63 data input / output cb0 C cb7 ecc check bits dm0 C dm8 input data mask dqs0 C dqs 8 data strobe, positive line dqs0# - dqs 8 # data strobe, negative line (only used when differential data strobe mode is enabled) ras# row address strobe cas# column address strobe we# write enable cke0 C cke1 clock enable s0#, s1# chip select ck0 C ck1 clock inputs, positive line figure 1: mechanical dimensions
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 ck0# C ck1# clock inputs, negative line event# temperature event: the event# pin is asserted by the temperature sensor when critical v dd supply voltage ( 1.35v - 0.067v/+0.1v and 1.5v 0.075v) v ref dq reference voltage: dq, dm (v dd /2) v ref ca reference voltage: control, command, and address (v dd /2) v ss ground v tt termination voltage: used for control, command, and address (v dd /2). v ddspd serial eeprom positive power supply scl serial clock for presence detect sda serial data out for presence detect sa0 C sa2 presence detect address inputs odt0, odt1 on - die termination nc no connection pin configuration frontside pin symbol pin symbol pin symbol pin symbol pin symbol 1 v ref dq 27 dq18 49 nc(v tt ) 75 v dd 101 v ss 2 v ss 28 dq19 50 cke0 76 s1# 102 dqs6# 3 dq0 29 v ss 51 v dd 77 odt1 103 dqs6 4 dq1 30 dq24 52 ba2 78 v dd 104 v ss 5 v ss 31 dq25 53 nc(er r_out#) 79 nc(s2#) 105 dq50 6 dqs0# 32 v ss 54 v dd 80 v ss 106 dq51 7 dqs0 33 dqs3# 55 a11 81 dq32 107 v ss 8 v ss 34 dqs3 56 a7 82 dq33 108 dq56 9 dq2 35 v ss 57 v dd 83 v ss 109 dq57 10 dq3 36 dq26 58 a5 84 dqs4# 110 v ss 11 v ss 37 dq27 59 a4 85 dqs4 111 dqs7# 12 dq8 38 v ss 60 v d d 86 v ss 112 dqs7 13 dq9 39 cb0 61 a2 87 dq34 113 v ss 14 v ss 40 cb1 62 v dd 88 dq35 114 dq58 15 dqs1# 41 v ss 63 ck1 89 v ss 115 dq59 16 dqs1 42 dqs8# 64 c k1# 90 dq40 116 v ss 17 v ss 43 dqs8 65 v dd 91 dq41 117 sa0 18 dq10 44 v ss 66 v dd 92 v ss 118 scl 19 dq11 45 cb2 67 v re f ca 93 dqs5# 119 sa2 20 v ss 46 cb3 68 nc(par_in) 94 dqs5 120 v tt 21 dq16 47 v ss 69 v dd 95 v ss 22 dq17 48 nc(v tt ) 70 a10/ ap 96 dq42 23 v ss 71 ba0 97 dq43 24 dqs2# 72 v dd 98 v ss 25 dqs2 73 we# 99 dq48 26 v ss 74 cas# 100 dq49 signals in brackets () may be connected at the dimm socket, but are not used on the dimm
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 backside pin symbol pin symbol pin symbol pin symbol pin symbol 121 v ss 147 dq23 169 cke1 195 odt0 221 dm6(dqs15) 122 dq4 148 v ss 170 v dd 196 a13 222 nc(dqs15#) 123 dq5 149 dq28 171 a15) 197 v dd 223 v ss 124 v ss 150 dq29 172 a14 198 nc(s3#) 224 dq54 125 dm0(dqs9 ) 151 v ss 173 v dd 199 v ss 225 dq55 126 nc(dqs9#) 152 dm3(dqs12) 174 a12, bc# 200 dq36 226 v ss 127 v ss 153 nc(dqs12#) 175 a9 201 dq37 227 dq60 128 dq6 154 v ss 176 v dd 202 v ss 228 dq61 129 dq7 155 dq30 177 a8 203 dm4(dqs13) 229 v ss 130 v ss 156 dq31 178 a6 204 nc(dqs13#) 230 dm7(dqs16) 131 dq12 157 v ss 179 v dd 205 v ss 231 nc(dqs16#) 132 dq13 1 58 cb4 180 a3 206 dq38 232 v ss 133 v ss 159 cb5 181 a1 207 dq39 233 dq62 134 dm1(dqs10) 160 v ss 182 v dd 208 v ss 234 dq63 135 nc(dqs10#) 161 dm8(dqs17) 183 v dd 209 dq44 235 v ss 136 v ss 162 nc(dqs17#) 184 ck0 210 dq45 236 v ddspd 137 dq1 4 163 v ss 185 ck0# 211 v ss 237 sa1 138 dq15 164 cb6 186 v dd 212 dm5(dqs14) 238 sda 139 v ss 16 5 cb7 187 event# 213 nc(dqs14#) 239 v ss 140 dq20 166 v ss 188 a0 214 v ss 240 v tt 141 dq21 167 nc(test) 189 v dd 215 dq46 142 v ss 168 reset# 190 ba1 216 dq47 143 dm2(dqs11) 191 v dd 217 v ss 144 nc(dqs11#) 192 ras# 218 dq52 145 v ss 193 s0# 219 dq53 146 dq22 194 v dd 220 v ss signals in brackets () may be connected at the dimm socket, but are not used on the dimm
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 functional block diagramm 8192 mb ddr3 sdram dimm, 2 ranks and 1 8 components dq 0 dq 1 dq 2 dq 3 dq 5 dq 4 dq 6 dq 7 s 0 dqs 0 dqs 0 dm 0 dqs 1 dqs 1 dm 1 dq 8 dq 9 dq 10 dq 11 dq 13 dq 12 dq 14 dq 15 dqs 2 dqs 2 dm 2 dq 16 dq 17 dq 18 dq 19 dq 21 dq 20 dq 22 dq 23 dqs 3 dqs 3 dm 3 dq 24 dq 25 dq 26 dq 27 dq 29 dq 28 dq 30 dq 31 dq 32 dq 33 dq 34 dq 35 dq 37 dq 36 dq 38 dq 39 dqs 4 dqs 4 dm 4 dqs 5 dqs 5 dm 5 dq 40 dq 41 dq 42 dq 43 dq 45 dq 44 dq 46 dq 47 dqs 6 dqs 6 dm 6 dq 48 dq 49 dq 50 dq 51 dq 53 dq 52 dq 54 dq 55 dqs 7 dqs 7 dm 7 dq 56 dq 57 dq 58 dq 59 dq 61 dq 60 dq 62 dq 63 v ddspd spd v dd / v ddq d 0 - d 17 v refdq v refca d 0 - d 17 d 0 - d 17 d 0 - d 17 v ss ck 0 , ck 1 notes : 1 . dq - to - i / o wiring is shown as recommended but may be changed . 2 . dq / dqs / dqs / odt / dm / cke / s relationship must be maintained as shown . 3 . dq , dm , dqs / dqs resistors : refer to associated topology diagram . 4 . refer to the appropriate clock wiring topology under the dimm wiring details section of the jeded document . 5 . for each dram , a unique zq resistor is connected to gnd . the zq resistor is 240 o 1 %. 6 . refer to associated figure for spd details . i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 0 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 9 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 1 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 10 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 2 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 11 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 3 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 12 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 4 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 13 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 5 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 14 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 6 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 15 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 7 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 16 dqs cs s 1 cb 0 cb 1 cb 2 cb 3 cb 5 cb 4 cb 6 cb 7 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 8 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 17 dqs cs ba 0 - ba 2 ba 0 - ba 2 : sdram d 0 - d 17 a 0 - a 15 a 0 - a 15 : sdram d 0 - d 17 ras ras : sdram d 0 - d 17 cas cas : sdram d 0 - d 17 we we : sdram d 0 - d 17 odt 0 odt : sdram d 0 - d 8 cke 1 cke : sdram d 9 - d 17 ck : sdram d 0 - d 17 ck 0 , ck 1 ck : sdram d 0 - d 17 reset reset : sdram d 0 - d 17 cke 0 cke : sdram d 0 - d 8 odt 1 odt : sdram d 9 - d 17 dqs 8 dm 8 dqs 8
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 maximum electrical dc characteristics parameter/ condition symbol min max units v dd supply voltage relative to v ss v dd - 0.4 1.975 v i/o v dd supply voltage relative to v ss v dd q - 0.4 1.975 v voltage on any pin relative to v ss v in , v out - 0.4 1.975 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 16 16 ck, ck# - 16 16 dm - 2 2 output leakage current (dqs and odt are disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 8 8 a ddr3l (1.35v) dc operating conditions parameter/ condition symbol min nom max units parameter/ condition symbol min nom max units supply voltage v dd 1.283 1.35 1.450 v i/o supply voltage v dd q 1.283 1.35 1.450 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt 0.49 x v dd q - 20mv 0.50 x v dd q 0.51x v dd q +20mv v input high (logic 1) voltage v ih (dc 90 ) v ref + 90mv v dd q + 0.3 v ddr3 (1.50v) dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.425 1.5 1.575 v i/o supply voltage v dd q 1.425 1.5 1.575 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt 0.49 x v dd q - 20mv 0.50 x v dd q 0.51x v dd q +20mv v input high (logic 1) voltage v ih (dc) v ref + 0.1 v dd q + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.175 - v input low (logic 0) voltage v il (ac) - v ref - 0.175 v capacitance at ddr3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets.
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 i dd specifications and conditions (0c t case + 85c, v dd q = +1.35v, v dd = +1.35v ) parameter & test condition symbol max. unit 12800 cl11 10600 cl9 operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between valid commands; dq inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 324 315 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 414 396 ma precharge power - down current: all device banks idle; power - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast exit i dd2p 144 144 ma slow exit 144 144 precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all control and address bus inputs are not changing; dqs are floating at v ref i dd2q 180 180 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd2n 198 198 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref (always fast exit) i dd3p 198 198 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd3n 378 360 ma operating read current: all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 684 603 ma
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 parameter & test condition symbol max. unit 12800 cl11 10600 cl9 operating write current: all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4w 684 603 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 1782 1782 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are floating at v ref ; dqs are floating at v ref i dd6 216 216 ma operating current*) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1206 1179 ma *) value calculated as one module rank in this operating condition, and all other module ranks in idd2p (cke low) mode. timing values used for i dd measurement i dd measurement conditions symbol 12800 cl11 10600 cl9 unit cl (i dd ) 11 9 t ck t rcd (i dd ) 13.75 13.5 ns t rc (i dd ) 48.75 49.5 ns t rrd (i dd ) 6.25 6 ns t ck (i dd ) 1.25 1.5 ns t ras min (i dd ) 35 36 ns t ras max (i dd ) 70200 70200 ns t rp (i dd ) 13.75 13.5 ns t rfc (i dd ) 260 260 t ck
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 ddr3 sdram component electrical characteristics and recommended ac operating conditions (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 12800 cl11 10600 cl9 parameter symbol min max min max unit clock cycle time cl = 11 t ck (11) 1.25 1.5 - - ns cl = 10 t ck (10) 1.5 <1.875 1.5 <1.875 ns cl = 9 t ck (9) 1.5 <1.875 1.5 <1.875 ns cl = 8 t ck (8) 1.875 < 2.5 1.875 <2.5 ns cl = 7 t ck (7) 1.875 <2.5 1.875 <2.5 ns cl = 6 t ck (6) 2.5 3.3 2.5 3.3 ns cl = 5 t ck (5) 3.0 3.3 3.0 3.3 ns read cmd to 1 st data t aa 13.75 - 13.5 - ns ck high - level width t ch (avg) 0.47 0.53 0.47 0.53 t ck ck low - level width t cl ( avg) 0.47 0.53 0.47 0.53 t ck data - out high - impedance window from ck/ck# t hz - 225 - 250 ps data - out low - impedance window from ck/ck# t lz - 450 225 - 500 250 ps dq and dm input pulse width ( for each input ) t dipw 360 - 400 - ps dq - dqs hold, dqs to first dq to go non - valid, per access t qh 0.38 - 0.38 - t ck (avg) dqs input high pulse width t dqsh 0.45 0.55 0.45 0.55 t ck dqs input low pulse width t dqsl 0.45 0.55 0.45 0.55 t ck dqs read preamble t rpre 0.9 note 1 0.9 note 1 t ck dqs read postamble t rpst 0.3 note 2 0.3 note 2 t ck dqs write preamble t wpre 0.9 - 0.9 - t ck dqs write postamble t wpst 0.3 - 0.3 - t ck 1 the maximum preamble is bound by t lzdqs (max) 2 the maximum postamble is bound by t hzdqs (max) the dq, dqs setup and hold times as well as command/address setup and hold times need to be calculated using the respective component data sheets with derating tables and the driver slew rate in combination with the jedec min/max routing information
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 ddr3 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 12800 cl11 10600 cl9 parameter symbol min max min max unit cas# to cas# command delay t ccd 4 - 4 - t ck active to active (same bank) command period t rc 48.75 - 49.5 - ns active bank a to active bank b command t rrd max 4nck,6ns - max 4nck, 6 ns - ns active to read or write delay t rcd 13.75 - 13.5 - ns four bank activate period 1k page size t faw 30 - 30 - ns 2k page size 40 - 45 - active to precharge command t ras 35 70200 70200 t rtp max 4nck,7.5ns - max 4nck,7.5ns - ns write recovery time t wr 15 - 15 - ns auto precharge write recovery + precharge time t dal t wr + t rp /t ck - t wr + t rp /t ck - ns internal write to read command delay t wtr max 4nck,7.5ns - max 4nck,7.5ns - ns precharge command period t rp 13.75 - 13.5 - ns load mode command cycle time t mrd 4 - 4 - t ck refresh to active or refresh to refresh command interval t rfc 260 70200 70200 0 c t case 85 c t refi - 7.8 - 7.8 s 85 c < t case 95 c t refi (it) - 3.9 - 3.9 rtt turn - on from odtl on reference t aon - 2 25 2 25 - 250 250 ps rtt turn - on from odtl off reference t aof 0.3 0.7 0.3 0.7 t ck asynchronous rtt turn - on delay (power down with dll off) t aonpd 2 8,5 2 8,5 ns asynchronous rtt turn - off delay (power down with dll off) t aofpd 2 8,5 2 8,5 ns rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 t ck first dqs, dqs# rising edge t wlmrd 40 - 40 - t ck dqs, dqs# delay t wldqsen 25 - 25 - t ck
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 ddr3 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 12800 cl11 10600 cl9 parameter symbol min max min max unit exit reset from cke high to a valid command t xpr max 5nck, t rfc + 10ns - max 5nck, t rfc + 10ns - t ck begin power supply ramp to power supplies stable t v ddpr - 200 - 200 ms reset# low to power supplies stable t rps 0 200 - 200 ms reset# low to i/o and rtt high - z t ioz - 20 - 20 ns exit precharge power - down to any non - read command t xp max 3nck,6ns - max 3nck,6ns - t ck cke minimum high/low time t cke max 3nck, 5 ns - max 3nck, 5.625ns - t ck temperature sensor with serial presence - detect eeprom temperature sensor with serial presence - detect eeprom operating conditions parameter / condition symbol min max unit supply voltage v ddspd +3 +3.6 v supply current: v dd = 3.3v i dd +2.0 ma input high voltage: logic 1; scl, sda v ih +1.45 v ddspd +1 v input low voltage: logic 0; scl, sda v il - 550 mv output low voltage: i out = 2.1ma v ol - 400 mv input current i in - 5.0 5.0 a temperature sensing range t . b . d t . b . d c temperature sensor accuracy t . b . d t . b . d c s c l s d a e v e n t s a 2 s a 2 s a 1 s a 1 s a 0 s a 0 e v e n t w p / r 1 0
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 serial presence - detect matrix byte byte description 12800 cl11 10600 cl9 0 crc range, eeprom bytes, bytes used 0x92 1 spd revison 0x1 2 2 dram device type 0x0b 3 module type (form factor) 0x02 4 sdram device density & banks 0x0 4 5 sdram device row & column count 0x 21 6 byte 6 reserved 0x0 2 7 module ranks & device dq count 0x09 8 ecc tag & module memory bus width 0x0 b 9 fine timebase dividend/divisor 0x 11 10 medium timebase dividend 0x01 11 medium timebase divisor 0x08 12 min sdram cycle time (t ck min ) 0x0a 0x0c 13 byte 13 reserved 0x00 14 cas latencies supported (cl4 => cl11) 0 xfe 0x3 e 15 cas latencies supported (cl12 => cl18) 0x00 16 min cas latency time (t aa min ) 0x69 17 min write recovery time (t wr min ) 0x78 18 min ras# to cas# delay (t rcd min ) 0x69 19 min row active to row active delay (t rrd min ) 0x30 20 min row precharge delay (t rp min ) 0x69 21 upper nibble for t ras & t rc 0x11 22 min active to precharge delay (t ras min ) 0x18 0x20 23 min active to active/refresh delay (t rc min ) 0x81 0x89 24 min refresh recovery delay (t rfc min ) lsb 0x 20 25 min refresh recovery delay (t rfc min ) msb 0x 0 8 26 min int ernal write to read cmd delay (t wtr min ) 0x3c 27 min interna l read to precharge cmd delay (t rtp min ) 0x3c 28 min four active window delay (t faw min ) msb 0x00 29 min four active window delay (t faw min ) lsb 0xf0 30 sdram device output drivers supported 0x8 3 31 sdram device thermal & refresh options 0x0 1
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 byte byte description 12800 cl11 10600 cl9 32 ddr3 - module thermal sensor 0x80 33 - 59 bytes 32 - 59 reserved 0x00 60 module height (nominal) 0x0 3 61 module thickness (max) 0x11 62 reference raw card id (rc k 1) 0x 09 63 address mapping edge conector to dram 0x01 64 - 116 bytes 64 - 116 reseved 0x00 117 module mfr id (lsb) 0x83 118 module mfr id (msb) 0xda 119 module mfr location id 0x01 (switzerland) 0x02 (germany) 0x03 (usa) 120 module mfr year x 121 module mfr week x 122 - 125 module serial number x 126 - 127 crc 0xd1fb 0 x e524 128 - 145 module part number "s l u0 8g72 k1bd 2sa - xx" 146 module die rev x 147 module pcb rev x 148 dram device mfr id (lsb) 0x80 149 dram device mfr (msb) 0xce 150 - 175 mfr reserved bytes 150 - 175 0xff 176 - 255 customer reserved bytes 176 - 255 0xff part number code s l u 0 8 g 72 k1 b d 2 sa - dc * r ** 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ** thermal sensor *rohs compl. s wissbit ag ddr3 - 1 600 mt/s sdram ddr3 l 2 40 pin u dimm chip vendor ( samsung ) c apacity ( 8 gb yte ) 2 module ranks width ( 72 bit) chip rev. d pcb - type ( d3u28k ) chip organisation x8 * optional / additional information
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 revision history revision changes date 1.0 first release 17.02.2014
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 15 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 locations swissbit ag industriestrasse 4 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 1117 e plaza drive unit e suites 105/205 eagle, id 83616 usa phone: +1 208 258 - 6254 fax: +1 208 938 - 4525 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, suginami - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512 ________________________________
data sheet rev.1.0 17.02.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 16 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 declaration of conformity we manufacturer: swissbit ag industriestrasse 4 ch - 9552 bronschhofen switzerland declare under our sole responsibility that the product product type: 8 gb ddr3 l ecc udimm brand name: swissmemory? product series: ddr3 l udimm part number: s l u0 8 g 72 k1 b d 2sa - xxxr t to which this declaration relates is in conformity with the following directives: 2002/96/ec category 3 (weee) following the provisions of directive restriction of the use of certain hazardous substances 2011/65/eu swissbit ag, february 2014 manuela k?gel head of quality management

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